The invention relates to a register for a serial stream of coded data provided with means for recognizing spurious pulses deriving from a peak detection process of reading data recorded on a mass storage support, in order to provide an output serial stream of coded data, purged of bits that are recognized as invalid.
When reading coded data recorded on mass memory (e.g., a hard disk), besides useful signals, the reading pick-ups detect: a) noise due to variations of physical parameters of the recording support and of the pick-ups, b) the so-called thermal noise and c) noise due to interferences among data recorded on tracks adjacent to the one being read by the pick-up.
With an increase in packing density of recording tracks, the noise due to interference phenomena among data recorded on adjacent tracks increases to a point of transforming itself from indeterministic to deterministic. As a consequence, the signal output by the reading pick-up may contain spurious peaks due to bits ("1") recorded on tracks adjacent to the one being read by the pick-up, which superimpose or interpose themselves on or between the peaks corresponding to the "1" relative to the data being read from the recording support.
According to common techniques with which data are recorded on a support such as a hard disk, the signal, filtered from pick-up noise, should be composed ideally of a sequence of peaks, alternately of opposite polarity, corresponding to logic "1" of coded data that are recorded on the track being read, "spaced" by intervals without peaks, corresponding to the logic "0". (See generally C. Mee et al., MAGNETIC RECORDING HANDBOOK (1989), which is hereby incorporated by reference. Relevant block diagrams may be found in the section Read Channel of the "Storage Product 1993 Data Book" of Silicon Systems (e.g. in relation to devices SSI32P4731 and SSI32P474).)
In order to curb the effects of noise, the peaks detected by the pick-up may be accepted, or "qualified", when their amplitude extend beyond a certain fixed threshold level, positive or negative. When the noise component due to interferences caused by recordings present on adjacent tracks becomes prevailing, a peak qualification technique based on fixed thresholds, may introduce errors if interference peaks cause the instantaneous signal's amplitude to become larger than the respective threshold, positive or negative, as depicted in FIG. 1.
Under conditions of strong inter-track interference, a peak qualification system which is based on a variable threshold has proved itself more effective. The system qualifies a detected peak of the same sign of the last detected peak only if its level is greater than the level of the last detected peak, while the qualification is automatic if the detected peak is of opposite sign of the last detected peak. The effects of a variable threshold system (Adaptive Threshold Qualifier) are depicted in FIG. 2.
As may be easily observed in FIG. 2, in case successive peaks of the same polarity are qualified (positive polarity in the shown example), the peak having the greatest probability of being correct is the last one because of amplitude necessarily greater than a preceding peak or preceding peaks of the same sign.
In practice, a variable threshold qualification circuit (ATQ) produces two streams of digital data: qualified positive peaks correspond to the logic "1" of a first stream (SWP), while qualified negative peaks correspond to the logic "1" of a second stream (SWN). Of course, disregarding spurious peaks that may be qualified by the qualification circuit (ATQ), the output serial stream of coded data is simply given by the logic sum of the two digital data streams (SWP and SWN). In case of spurious peaks qualification it is necessary to eliminate the "1" recognized as spurious.
The system requires the use of special circuits for eliminating the spurious pulses deriving from the detection of spurious peaks by the reading pick-ups, the presence of which may be recognized by a simultaneous presence of more than one pulse of the same polarity between two pulses of opposite polarity. Moreover, a variable threshold qualification system allows the system to consider as valid the last one of such a sequence of pulses of same polarity and therefore to eliminate all but the last pulse.
A system of this type is described in Chopra et al., "A Soft Decision Method for Run-Length Limited Recording Channels," presented at the 24th ACSSC in 1990, which is hereby incorporated by reference.
A main objective of the present invention is to provide a survival sequence register (SSR), having a simple architecture and a great reliability, capable of processing the two serial data streams produced by a variable threshold circuit (ATQ), eventually recognizing in either one or the other stream a succession of pulses that may be attributed to the picking-up of peaks of the same polarity by a reading pick-up and therefore eliminating all the pulses of the "monopolar" (sequence) with the exception of the last one detected in order of time by the reading pick-up.
The system of the invention is based upon the recognition of an illicit succession due to the presence of pulses derived from the picking-up of peaks of the same polarity and on the consequent cancellation of spurious "1" from the serial stream of coded data, corresponding to the logic sum of the two streams produced by the variable threshold qualification circuit (ATQ), shifting through a register capable of storing a sufficient "depth" of the sequence of coded serial data in order that the shift register always contains at least a logic "1", depending upon the write/read coding that is employed.
Cancellation of spurious "1" from a sequence stored in the shift register, because identified as due to the reading of spurious peaks by the reading pick-up and qualified by the ATQ circuit, takes place by resetting the relative flip-flop of the shift register through a logic gate, having at least three inputs, that drives the reset terminal of the flip-flop.
An erase signal, generated by a circuit capable of recognize a succession of pulses ("1") corresponding to detected peaks of the same polarity, that are not intermeshed with peaks of opposite polarity, is eventually applied to a first input of the erasing logic gate.
A signal, derived from a corresponding tap of a second (pointer) register that points a spurious "1" to be cancelled from the sequence stored in the first shift register, is fed to a second input of the erasing logic gate.
A disabling signal, derived from the Q output of the same flip-flop that is reset by the respective logic gate, is applied to a third input thereof. By such a fed-back signal, the erasing logic gate is self-synchronized, by having its activated output only for the time necessary to erase the spurious bit ("1"), pointed by the pointer register. As soon as the spurious bit has been cancelled, the erasing gate is disabled and therefore the cancellation input that is applied to the flip-flop through its reset terminal terminates.
The duration of the erase input is therefore positively less than the clock period, thus avoiding the loss of data during the shifting through the shift register of a correct sequence of bits.